As semiconductive devices continue to shrink and component density rises, the conventional dielectrics that have been used in the past have begun to run into limitations. One such limitation is the dielectric capacitance that inherently exists within every semiconductive device due to the presence of the dielectric layers that electrically isolate interconnects and the transistors from each other. With device miniaturization, interconnect capacitive effects are becoming more prominent and problematic than before. This is due in part to the interconnect speed performance, which is directly proportional to the product of the dielectric capacitance and conducting metal resistance. Thus, with the continued miniaturization and increased densification of interconnects, the semiconductive industry is currently moving toward the use of low dielectric (low-k) materials to electrically insulate interconnects for semiconductive devices to reduce capacitive delays associated with the higher dielectric constant of silicon dioxide.
While the dielectrics presently being used by the semiconductive industry have dielectric constants less than that of silicon dioxide (i.e., less than about 4.0), it has been found that materials having lower and lower dielectric constants must be used with the progression to the next smaller node size. As a result, there is a constant struggle for semiconductive device manufacturers to find materials that will provide a lower dielectric constant with each new generation of node size.
Additionally, interconnect resistance has risen due to a decrease in interconnect line widths. Further, the increased interconnect line density has almost doubled the total length of metal lines present in these smaller devices. Moreover, in the past when metal lines were wider, the current transmission resided more within the center of the line, which has less resistance associated with it. However, as the line dimensions have shrunk, the electrical transmission now occupies nearly the entire dimension of the line, which enhances charge carrier scattering effects and, in turn, significantly increases total resistance. Both the added length and increased resistance at smaller line widths adds additional resistance to the device. The industry is presently struggling with how to best compensate for this increase in metal resistance. Since interconnect delays are related to the product of dielectric capacitance and metal resistance, the industry is looking for ways to decrease the interlevel dielectric capacitance as technology evolves into smaller devices.
Accordingly, what is needed in the art is a semiconductive device and method of manufacturing that device that provides the lowest interlevel dielectric capacitance possible.